Instruction Reference

These tables provide summaries for the baseline RISC-V instructions and common extensions. Full specifications be found on the RISC-V website. Additionally, more details about each instruction can be found here.

Pseudo Instructions

These pseudo-instructions represent additional actions and can be used like regular instructions. One of the early passes in the assembler will transform them as described in this table.

Instruction	Expansion	Description
nop	addi x0, x0, 0	No operation
li rd, imm	See below	Load immediate
mv rd, rs	addi rd, rs, 0	Copy register
not rd, rs	xori rd, rs, -1	One’s complement
neg rd, rs	sub rd, x0, rs	Two’s complement
seqz rd, rs	sltiu rd, rs, 1	Set if == zero
snez rd, rs	sltu rd, x0, rs	Set if != zero
sltz rd, rs	slt rd, rs, x0	Set if < zero
sgtz rd, rs	slt rd, x0, rs	Set if > zero
beqz rs, offset	beq rs, x0, offset	Branch if == zero
bnez rs, offset	bne rs, x0, offset	Branch if != zero
blez rs, offset	bge x0, rs, offset	Branch if <= zero
bgez rs, offset	bge rs, x0, offset	Branch if >= zero
bltz rs, offset	blt rs, x0, offset	Branch if < zero
bgtz rs, offset	blt x0, rs, offset	Branch if > zero
bgt rs, rt, offset	blt rt, rs, offset	Branch if >
ble rs, rt, offset	bge rt, rs, offset	Branch if <=
bgtu rs, rt, offset	bltu rt, rs, offset	Branch if > (unsigned)
bleu rs, rt, offset	bgeu rt, rs, offset	Branch if <= (unsigned)
j offset	jal x0, offset	Jump
jal offset	jal x1, offset	Jump and link
jr rs	jalr x0, 0(rs)	Jump register
jalr rs	jalr x1, 0(rs)	Jump and link register
ret	jalr x0, 0(x1)	Return from subroutine
call offset	See below	Call far-away subroutine
tail offset	See below	Tail call far-away subroutine
fence	fence iorw, iorw	Fence on all memory and I/O

Expansion of li rd, imm

Depending on the value of the imm, li may get expanded into a few different combinations of instructions.

Criteria	Expansion
imm between [-2048, 2047]	addi rd, x0, %lo(imm)
imm & 0xfff == 0	lui rd, %hi(imm)
otherwise	lui rd, %hi(imm) addi rd, rd, %lo(imm)

Expansion of call offset

Depending on how near / far away the label referred to by offset is, call may get expanded into a few different combinations of instructions.

Criteria	Expansion
offset is near	jal x1, %lo(offset)
otherwise	auipc x1, %hi(offset) jalr x1, x1, %lo(offset)

Expansion of tail offset

Depending on how near / far away the label referred to by offset is, tail may get expanded into a few different combinations of instructions.

Criteria	Expansion
offset is near	jal x0, %lo(offset)
otherwise	auipc x6, %hi(offset) jalr x0, x6, %lo(offset)

RV32I Base Instruction Set

Instruction	Description
lui rd, imm	load upper 20 bits of rd with 20-bit imm, fill lower 12 bits with zeroes
auipc rd, imm	load upper 20 bits of pc with 20-bit imm, fill lower 12 bits with zeroes, add this offset to addr of this instruction and store into rd
jal rd, imm	jump offset 20-bit MO2 imm and store return addr into rd
jalr rd, rs1, imm	jump offset 12-bit MO2 imm plus rs1 and store return addr into rd
beq rs1, rs2, imm	jump offset 12-bit MO2 imm if rs1 is equal to rs2
bne rs1, rs2, imm	jump offset 12-bit MO2 imm if rs1 is not equal to rs2
blt rs1, rs2, imm	jump offset 12-bit MO2 imm if rs1 is less than rs2
bge rs1, rs2, imm	jump offset 12-bit MO2 imm if rs1 is greater than or equal to rs2
bltu rs1, rs2, imm	jump offset 12-bit MO2 imm if rs1 is less than rs2 (unsigned)
bgeu rs1, rs2, imm	jump offset 12-bit MO2 imm if rs1 is greater than or equal to rs2 (unsigned)
lb rd, rs1, imm	load 8-bit value from addr in rs1 plus 12-bit imm into rd (sign extend)
lh rd, rs1, imm	load 16-bit value from addr in rs1 plus 12-bit imm into rd (sign extend)
lw rd, rs1, imm	load 32-bit value from addr in rs1 plus 12-bit imm into rd
lbu rd, rs1, imm	load 8-bit value from addr in rs1 plus 12-bit imm into rd (zero extend)
lhu rd, rs1, imm	load 16-bit value from addr in rs1 plus 12-bit imm into rd (zero extend)
sb rs1, rs2, imm	store 8-bit value from rs2 into addr in rs1 plus 12-bit imm
sh rs1, rs2, imm	store 16-bit value from rs2 into addr in rs1 plus 12-bit imm
sw rs1, rs2, imm	store 32-bit value from rs2 into addr in rs1 plus 12-bit imm
addi rd, rs1, imm	add 12-bit imm to rs1 and store into rd
slti rd, rs1, imm	store 1 into rd if rs1 is less than 12-bit imm else store 0
sltiu rd, rs1, imm	store 1 into rd if rs1 is less than 12-bit imm (unsigned) else store 0
xori rd, rs1, imm	bitwise XOR 12-bit imm with rs1 and store into rd
ori rd, rs1, imm	bitwise OR 12-bit imm with rs1 and store into rd
andi rd, rs1, imm	bitwise AND 12-bit imm with rs1 and store into rd
slli rd, rs1, shamt	shift rs1 left by shamt bits and store into rd
srli rd, rs1, shamt	shift rs1 right by shamt bits and store into rd (shift in zeroes)
srai rd, rs1, shamt	shift rs1 right by shamt bits and store into rd (shift in sign bit)
add rd, rs1, rs2	add rs2 to rs1 and store into rd
sub rd, rs1, rs2	subtract rs2 from rs1 and store into rd
sll rd, rs1, rs2	shift rs1 left by rs2 bits and store into rd
slt rd, rs1, rs2	store 1 into rd if rs1 is less than rs2 else store 0
sltu rd, rs1, rs2	store 1 into rd if rs1 is less than rs2 (unsigned) else store 0
xor rd, rs1, rs2	bitwise XOR rs2 with rs1 and store into rd
srl rd, rs1, rs2	shift rs1 right by rs2 bits and store into rd (shift in zeroes)
sra rd, rs1, rs2	shift rs1 right by rs2 bits and store into rd (shift in sign bit)
or rd, rs1, rs2	bitwise OR rs2 with rs1 and store into rd
and rd, rs1, rs2	bitwise AND rs2 with rs1 and store into rd
fence succ, pred	order device I/O and memory accesses
ecall	make a service request to the execution environment
ebreak	return control to a debugging environment

RV32M Standard Extension

Instruction	Description
mul rd, rs1, rs2	multiply rs1 (signed) by rs2 (signed) and store lower 32 bits into rd
mulh rd, rs1, rs2	multiply rs1 (signed) by rs2 (signed) and store upper 32 bits into rd
mulhsu rd, rs1, rs2	multiply rs1 (signed) by rs2 (unsigned) and store upper 32 bits into rd
mulhu rd, rs1, rs2	multiply rs1 (unsigned) by rs2 (unsigned) and store upper 32 bits into rd
div rd, rs1, rs2	divide (signed) rs1 by rs2 and store into rd
divu rd, rs1, rs2	divide (unsigned) rs1 by rs2 and store into rd
rem rd, rs1, rs2	remainder (signed) of rs1 divided by rs2 and store into rd
remu rd, rs1, rs2	remainder (unsigned) of rs1 divided by rs2 and store into rd

RV32A Standard Extension

All of the following atomic instructions also accept two additional parameters: aq and rl. These are short for “acquire” and “release” and must either be both specified or both unspecified. The default for each if unspecified is zero.

For example:

# both aq and rl are zero
lr.w t0 t1
lr.w t0 t1 0 0

# both aq and rl are one
lr.w t0 t1 1 1

# mix and match
lr.w t0 t1 0 1  # aq=0, rl=1
lr.w t0 t1 1 0  # aq=1, rl=0

Instruction	Description
lr.w rd, rs1	load (reserved) 32-bit value from addr in rs1 into rd and register a reservation set
sc.w rd, rs1, rs2	store (conditional) 32-bit value from rs2 into addr in rs1 and write status to rd
amoswap.w rd, rs1, rs2	atomically load value from addr in rs1 into rd, SWAP with value in rs2, store back to addr rs1
amoadd.w rd, rs1, rs2	atomically load value from addr in rs1 into rd, ADD to value in rs2, store back to addr rs1
amoxor.w rd, rs1, rs2	atomically load value from addr in rs1 into rd, XOR with value in rs2, store back to addr rs1
amoand.w rd, rs1, rs2	atomically load value from addr in rs1 into rd, AND with value in rs2, store back to addr rs1
amoor.w rd, rs1, rs2	atomically load value from addr in rs1 into rd, OR with value in rs2, store back to addr rs1
amomin.w rd, rs1, rs2	atomically load value from addr in rs1 into rd, MIN with value in rs2, store back to addr rs1
amomax.w rd, rs1, rs2	atomically load value from addr in rs1 into rd, MAX with value in rs2, store back to addr rs1
amominu.w rd, rs1, rs2	atomically load value from addr in rs1 into rd, MIN (unsigned) with value in rs2, store back to addr rs1
amomaxu.w rd, rs1, rs2	atomically load value from addr in rs1 into rd, MAX (unsigned) with value in rs2, store back to addr rs1

RV32C Standard Extension

Instruction	Description
c.addi4spn rd', nzuimm	add 8-bit MO4 nzuimm to x2/sp and store into rd'
c.lw rd', rs1', uimm	load 32-bit value from addr in rs1' plus 5-bit MO4 uimm into rd'
c.sw rs1', rs2', uimm	store 32-bit value from rs2' into addr in rs1' plus 5-bit MO4 uimm
c.nop	no operation
c.addi rd/rs1!=0, nzimm	add 6-bit imm to rd/rs1 and store into rd/rs1
c.jal imm	jump offset 11-bit MO2 imm and store return addr into x1/ra
c.li rd!=0, imm	load 6-bit imm into rd, sign extend upper bits
c.addi16sp nzimm	add 6-bit MO16 nzimm to x2/sp and store into x2/sp
c.lui rd!={0,2}, nzimm	load 6-bit imm into middle bits [17:12] of rd, sign extend upper bits, clear lower bits
c.srli rd'/rs1', nzuimm	shift rd'/rs1' right by nzuimm bits and store into rd'/rs1' (shift in zeroes)
c.srai rd'/rs1', nzuimm	shift rd'/rs1' right by nzuimm bits and store into rd'/rs1' (shift in sign bit)
c.andi rd'/rs1', imm	bitwise AND 6-bit imm with rd'/rs1' and store into rd'/rs1'
c.sub rd'/rs1', rs2'	subtract rs2' from rd'/rs1' and store into rd'/rs1'
c.xor rd'/rs1', rs2'	bitwise XOR rs2' with rd'/rs1' and store into rd'/rs1'
c.or rd'/rs1', rs2'	bitwise OR rs2' with rd'/rs1' and store into rd'/rs1'
c.and rd'/rs1', rs2'	bitwise AND rs2' with rd'/rs1' and store into rd'/rs1'
c.j imm	jump offset 11-bit MO2 imm
c.beqz rs1', imm	jump offset 8-bit MO2 imm if rs1' is equal to zero
c.bnez rs1', imm	jump offset 8-bit MO2 imm if rs1' is not equal to zero
c.slli rd/rs1!=0, nziumm	shift rd/rs1 left by nzuimm bits and store into rd/rs1
c.lwsp rd!=0, uimm	load 32-bit value from addr in x2/sp plus 6-bit MO4 uimm into rd
c.jr rs1!=0	jump to addr in rs1
c.mv rd!=0, rs2!=0	copy value from rs2 into rd
c.ebreak	return control to a debugging environment
c.jalr rs1!=0	jump to addr in rs1 and store return addr into x1/ra
c.add rd/rs1!=0, rs2!=0	add rs2 to rd/rs1 and store into rd/rs1
c.swsp rs2, uimm	store 32-bit value from rs2 into addr in x2/sp plus 6-bit MO4 uimm

“Zifencei” Standard Extension

Instruction	Description
fence.i	synchronize the instruction and data streams

“Zicsr” Standard Extension

Instruction	Description
csrrw rd, rs1, csr	atomically swap values in CSRs
csrrs rd, rs1, csr	atomically read and set bits in CSRs
csrrc rd, rs1, csr	atomically read and clear bits in CSRs
csrrwi rd, uimm, csr	atomically swap values in CSRs (immediate)
csrrsi rd, uimm, csr	atomically read and set bits in CSRs (immediate)
csrrci rd, uimm, csr	atomically read and clear bits in CSRs (immediate)